Edited by: B.H.V. Topping and P. Iványi

Keywords: Von Neumann barrier, next-generation processors, parallelism, multicore.

In this chapter we introduce the problems that motivate the design of the next generation processors. The continued increase of processor clock-speed is at all times crippled by inequal increasing relative time to access memory in the system. The problem, known as the Von Neumann bottleneck, has been bypassed for many years but now techniques like caching return increasingly poor benefit and new ideas are needed. The chapter looks into three different approaches to next-generation processors, the Niagara, the CELL-BE, and the Tesla, and how such processors may be programmed. In addition two approaches to programming such architectures, DSMCBE and CSP are briefly described and performance experiments are shown.

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